Field of the Invention
The present invention generally relates to semiconductor devices, and in particular to semiconductor devices having a carrier channel wherein structure for accelerating the carriers is provided.
With the progress in the lithographic patterning technique, field effect transistors having an extremely short gate length are becoming available. In such short gate length devices, a very large electric field is induced in the carrier channel in correspondence to a region located under the gate electrode and a large acceleration of carriers is achieved in such a region of increased electric field.
FIG. 1(A) shows a fundamental structure of a conventional MESFET and FIG. 1(B) shows the band diagram corresponding to the structure of FIG. 1(A).
Referring to FIG. 1(A), the MESFET comprises a substrate 10 of semi-insulating GaAs on which an n-type GaAs layer 12 is formed. The carrier channel is formed in this device layer 12. Thus, the layer 12 will be referred to hereinafter as a channel layer. In correspondence to the carrier channel, a gate electrode 14 is provided on the top surface of the channel layer 12, and source and drain electrodes 16 and 18 are provided on the top surface of the layer 12 at both sides of the gate electrode 14 as usual. Thus, the carriers are injected into the channel layer 12 via the source electrode 16 and transported along the channel in the layer 12 to a drain region formed under the drain electrode 18 under the control of a gate voltage applied to the gate electrode 14, and collected by the drain electrode 18 as a drain current.
FIG. 1(B) shows the band diagram of the device of FIG. 1(A) in the state where a source-drain voltage V.sub.sd is applied across the source and drain electrodes 16 and 18 and a source-gate voltage V.sub.sg is applied across the source and gate electrodes 16 and 14. In FIG. 1(B) the conduction band is designated by Ec and the valence band is designated by Ev. As can be seen in FIG. 1(B), the conduction band and the valence band are generally flat in the region between the source electrode 16 and the gate electrode 14 because the resistance of the channel between the source and gate electrodes is smaller than the resistance under the gate. On the other hand, the conduction band Ec and the valence band Ev are curved steeply in the region between the gate electrode 14 and the drain electrode 18 due to the large channel resistance under the gate. The carriers are accelerated by the large electric field associated with the large potential drop. This acceleration of carrier is particularly conspicuous in the region immediately under the gate electrode 14 and is enhanced further when the gate length is reduced. The reduction of the gate length increases the slope of the band and hence the electric field as will be easily understood.
FIG. 2 shows the effect of carrier overshoot that occurs when the gate length is reduced to increase the carrier velocity as reported by Ruch (J. G. Ruch, IEEE Trans. Electron Devices ED-19, pp. 652-654, 1972). As can be seen in this diagram, an overshoot occurs in the carrier velocity under high electric field when the gate length is reduced below 1 .mu.m. For example, it can be seen that a conspicuous overshoot is observed in the device having a gate length of less than 0.5 .mu.m when the electric field is increased to 10 kV/cm. Thereby, the carrier velocity is increased to a level more than three times greater than in the case where the device has a gate length larger than 1 .mu.m. When the carrier velocity is increased, the operational speed as well as the transconductance and cut-off frequency of the FET is increased.
In the conventional device of FIGS. 1(A) and 1(B), this feature of carrier overshoot is not exploited completely, since the acceleration of the carriers occurs after the carriers have passed under the gate electrode 14 in a direction toward the drain electrode 18. The acceleration of the carriers occurs after passing through the pinch-off point formed under the gate electrode 14 does not contribute significantly to the improvement of the operational characteristics. Further, it should be noted, as can be seen in the band diagram of FIG. 1(B), that the carriers are not accelerated substantially in the region of the channel between the source electrode 16 and the gate electrode 14. The conduction band Ec and the valence band Ev are generally flat in this region and thus, the electric field for accelerating the carriers is not formed. Further, the parasitic resistance of the channel layer 12, shown in FIG. 3(A) schematically as a resistor Rs, prevents high current injection into the channel under the gate. Thereby, the desired improvement of transconductance is not achieved even when there is a desirable overshoot of the carrier velocity in the part of the channel located immediately under the gate electrode 14.
In order to circumvent the latter problem, a self-aligned gate structure as shown in FIG. 3(B) is proposed. In this structure, doped source and drain regions 20a and 20b, doped to the n.sup.+ -type for example, are formed in the channel layer 12 by the ion implantation of impurities, using the gate electrode 14 as the mask. Thereby, the carrier density is increased in the regions 20a and 20b, leading to a decrease of the parasitic resistance Rs.
This conventional structure has a problem in that, because of the region of high carrier density formed adjacent to the gate electrode 14, the breakdown voltage across the gate electrode 14 and the drain electrode 18 tends to be deteriorated. Further, such a structure increases the parasitic capacitance between the gate and source represented schematically as C.sub.gs in FIG. 3(B). Thereby, the high frequency response of the transistor is inevitably deteriorated. Furthermore, the FETs having short gate lengths generally have the problem of deviation of the threshold voltage from the designed value.